A Time-Predictable Memory Network-on-Chip
نویسندگان
چکیده
To derive safe bounds on worst-case execution times (WCETs), all components of a computer system need to be time-predictable: the processor pipeline, the caches, the memory controller, and memory arbitration on a multicore processor. This paper presents a solution for timepredictable memory arbitration and access for chip-multiprocessors. The memory network-onchip is organized as a tree with time-division multiplexing (TDM) of accesses to the shared memory. The TDM based arbitration completely decouples processor cores and allows WCET analysis of the memory accesses on individual cores without considering the tasks on the other cores. Furthermore, we perform local, distributed arbitration according to the global TDM schedule. This solution avoids a central arbiter and scales to a large number of processors. 1998 ACM Subject Classification B.4.3 Interconnections (Subsystems)
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